1. Field of the Invention
The present invention relates to a semiconductor memory device which is electrically writable and has a nonvolatile property.
2. Description of the Prior Art
There is, for example, a nonvolatile semiconductor memory device that stores information by storing charges in a floating gate formed on a silicon substrate. Writing of information is realized by heightening a threshold value with respect to a control gate by storing charges in the floating gate, and erasion of information is realized by removing the charges from the floating gate.
The nonvolatile semiconductor memory device of this type has a phenomenon that the device is gradually deteriorated every time erasing/writing is conducted, and it is eventually impossible to do erasing or writing. The details will be described taking an EEPROM (electrically erasable programmable ROM) as an example.
FIG. 8 shows a change in minimum period of time required for erasing/writing when the EEPROM erasing/writing is repeated. As the erasing/writing is repeated, a period of time required for erasing/writing increases. In FIG. 8 is shown evaluation results of plural samples in which diffusion conditions are changed, and as is apparent from the figure, the number of times of writable operation largely changes according to the fluctuation at a manufacturing process.
For that reason, the limited number of times of writing operation is set taking the evaluation of the samples into account, and the operation is ensured within the limited number of times. The abnormal operation of erasing/writing causes information within the memory to be destroyed. Therefore, the lifetime is conventionally judged as described hereinafter.
To detect the lifetime of the nonvolatile semiconductor memory, the memory device is provided with a counter memory for holding the number of times of writing operation for every block which is a minimum unit that conducts writing and a counter for counting the number of times of writing operation and updating the counter memory using the count. An alarm signal is generated when the number of times of writing operation exceeds a predetermined number of times. Such a memory device is disclosed in Japanese Patent Application Laid-Open No. 7-254290.
More specifically, the operation is such that when data is written in a certain block, erasion is first made on all of memory cells within the block to set the contents of the memory cells at 0. Then, writing is made on only the memory cells the contents of which should be set at 1 within the block and the counter corresponding to the written block is incremented by 1. When the number of times of writing operation corresponding to any block exceeds a predetermined number of times. The alarm signal is generated to notify a user that the memory cell reaches its lifetime.
In the above-described method of setting the limited number of times of writing operation, the limited number of times of writing operation is found out by the evaluation of a product. And, when the limited number of times of writing operation reaches a given number of times of writing operation, it is judged that the memory device is at the end of its life.
Accordingly, there is developed a first problem because the lifetime is judged across the board according to not a deterioration state but a predetermined number of times of writing operation. In the case of setting the number of times of writing operation at a given limited value, it is judged that the memory cells can be used no longer regardless of the fact that the memory cells yet sufficiently functions. Since the memory cells have some fluctuation in manufacturing depending on manufacturing rods, the limited value of the number of times of writing operation must comply with the worst conditions. As a result, it is impossible to use the memory cells according to the characteristic thereof.
A second problem is to require a surplus memory, that is, the counter memory for holding the number of times of writing operation for each block. For example, in the case of counting up to 100,000 times, 17 memory cells (17 bits) are necessary for each block of the counter memory.